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Shilpa, K. S.
- Design of Standard Cell ASIC's Using Self Gated Resonant Clocked Flip Flop
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Authors
Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 2 (2017), Pagination: 385-388Abstract
Efforts to reduce power consumption of digital CMOS circuits have been in progress for nearly three decades. As a result, a number of well understood and proven techniques for reducing dynamic and leakage power have been developed. These methods are implemented thoroughly in the circuit level. So we have to shift our concentration towards high level circuits. One of the example for high level circuit is a standard cell Application Specific Integrated Circuit (ASIC). Reducing the power and delay of standard cell ASIC can improve the performance of the system designed using these. A major contributor to the total power in modern microprocessors is the clock distribution network, which can dissipate as much as 70% of the total power for high performance applications. Self-gated resonant-clocked flip-flop optimized for power efficiency and signal integrity achieves reduced dynamic power dissipation, in addition to the negative setup time, which makes the design more tolerant to the clock skew. This feature also reduces the D-Q delay, thus improving the timing performance of the flip-flop. The advantages of the Self gated resonant clocked flip-flop are implemented on standard cell ASICs. Cadence EDA tools and the 180nm process technology files have been used to substantiate the merits of the proposed design.Keywords
Application Specific Integrated Circuit (ASIC), SGR Clocked Flip-Flop.References
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- J.J.D. Jawahar, S.M.S. Murthy and K.B.V. Somasundaram, “Self-Gated Resonant-Clocked Flip-Flop Optimised for Power Efficiency and Signal Integrity”, IET Circuits, Devices & Systems, Vol. 10, No. 2, pp. 94-103, 2016.
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- Design Of High Performance Double Tail Comparator
Abstract Views :156 |
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Authors
Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 3 (2017), Pagination: 437-440Abstract
Comparator is an important building blocks used in analog-to-digital converters. Its function is to compare two analog inputs and delivers a logic value at the output. In this project an analysis on the delay of various dynamic comparators are presented. Based on the analysis a new dynamic comparator is designed for fast operations. Positive feedback mechanism is used to regenerate the analog input signal into full scale digital level. This design is a modification of conventional double-tail comparator. Addition of a few transistors to the conventional double-tail comparator results in remarkably reduced time delay. Kick-back noise of this comparator is also reduced. The large voltage variations in the internal nodes are coupled to the input nodes, which will disturb the input nodes-this is called kick-back noise. This is reduced by inserting switches before the input transistors of comparator. The performance of conventional comparator and proposed comparator circuits are evaluated based on Cadence 180nm CMOS process models.Keywords
Analog To Digital Converter (ADC), Double Tail Comparator, Kick Back Noise.References
- Samanesh Babayan-Mashhadi and Reza Lotfi, “Analysis and Design of a Low-Voltage-Power Double-Tail Comparator”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 22, No. 2, pp. 343-352, 2014.
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- Pedro M. Figueiredo and Joao C. Vital, “Kick-back Noise Reduction Techniques for CMOS Latched Comparators”, IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 53, No. 7, pp. 541-545, 2006.
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- Jun He, Sanyi Zhan, Degang Chen and Randall L. Geiger, “Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparatos”, IEEE Transactions on Circuits and Systems-I: Regular papers, Vol. 56, No. 5, pp. 911-919, 2009
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- Polyphenols in Cocoa Beans: A Potential Antioxidant
Abstract Views :381 |
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Authors
Affiliations
1 Cocoa Research Centre, Kerala Agricultural University, Vellanikkara, Thrissur (Kerala), IN
1 Cocoa Research Centre, Kerala Agricultural University, Vellanikkara, Thrissur (Kerala), IN
Source
International Journal of Agricultural Sciences, Vol 16, No 2 (2020), Pagination: 179-183Abstract
Cocoa (Theobroma cacao L.) is a potent source of polyphenol. There are reports that polyphenol and antioxidant activity is positively correlated. The present study investigated the total fat content, polyphenol content and antioxidant activity of cocoa beans obtained from twenty different cocoa hybrids. Folin – Ciocalteau (FC) reagent method was used to determine total polyphenol content in cocoa beans. Antioxidant activity was expressed as per cent radical scavenging activity and it was found out using DppH assay. Hybrid PIV 45.4 was found to be superior with respect to polyphenol content and antioxidant activity. Correlation studies revealed that total polyphenol content and antioxidant activity is positively correlated (r=0.613).Keywords
Cocoa, Theobroma cacao L., Hybrids, Polyphenol Content, Radical Scavenging Activity, Correlation.References
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